Digital Sawtooth Signal Generation with FPGA

Hello,

On my previous post, I explained how to create a sawtooth signal at 10kHz with a microcontroller (MSP430). Since it gave a discrete increase of the ramp due to low number of steps, 128 steps in that case, I tried to create a signal with higher frequency and higher number of steps accordingly.

For this purpose, I used a Nexys3 FPGA board which has a Spartan 6 Xilinx chip on it. Internal clock of this board is 100MHz, but to reach this speed from DIO pins, VHDC expansion connector must be used. There was no available connector for this interface, so I tried my best from Pmod connectors.

You can find the theoretical part from the the previous post, so I will skip that and directly explain the implementation. I used different from the previous version, I used TI DAC902U, which is essentially the same but has 12-bit parallel input capacity. The external connections are also the same.

The following figure shows the best available clock signal I could obtain from the Pmod connectors. It is not like a square wave, but works fine for my purpose. The frequency is 12.5 MHz, and a good point is that at least it is highly accurate and stable even though shape is not so good.

FPGA Clock Signal Output at 12.5 MHz

FPGA Clock Signal Output at 12.5 MHz

In the following figure you can see the connections between the FPGA Board and the DAC.

Nexys3 - DAC Connections

Nexys3 – DAC Connections

Verilog code for this counter is pretty simple. I have done it in behavioral style to reduce the work required. Moreover, there would not be any performance difference in such a small scale hardware description.

module Counter(
   input Clk,
   output [13:0] Count
   );

reg [13:0] Count;

   always@(negedge Clk) begin
      if(Count == 9999) Count = 0;
      Count = Count + 1;
   end

endmodule

Instead of creating a frequency divider and a counter separately (They are the same thing eventually.)  I built a 14-bit counter and used 12 most significant bits of it. 11 of those are the clock count from 0 to 1249 and the least significant one is the clock signal supply of the DAC.

Results:

Sawtooth Signal Output

Sawtooth Signal Output

A Closer Look to the Falling Edge

A Closer Look to the Falling Edge

There is an obvious improvement on both rising and falling edges of the signal. The rise is much smoother and the fall does not have that short peak to the negative voltages.

As always, you can contact me about anything related or unrelated to the post.

Thank you for your visit in my blog.

Gunay TURAN

p.s. I Have found such a contact form in the WordPress interface. Hope it will make it easier to contact me 🙂 I will add one of those to each post…

 

 

 

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